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Information on didactic, research and institutional assignments on this page are certified by the University; more information, prepared by the lecturer, are available on the personal web page and in the curriculum vitae indicated on this webpage.
Information
LecturerLevantino Salvatore
QualificationFull professor full time
Belonging DepartmentDipartimento di Elettronica, Informazione e Bioingegneria
Scientific-Disciplinary SectorIINF-01/A - Electronics
Curriculum VitaeDownload CV (466.75Kb - 05/02/2026)
OrcIDhttps://orcid.org/0000-0003-0895-1700

Contacts
Office hours
DepartmentFloorOfficeDayTimetableTelephoneFaxNotes
DEIB - edificio 22Quarto30Monday, WednesdayFrom 09:00
To 10:00
0223993731---Please take an appointment
E-mailsalvatore.levantino@polimi.it
Personal websitehttps://www.deib.polimi.it/ita/personale/dettagli/240258

Data source: RE.PUBLIC@POLIMI - Research Publications at Politecnico di Milano

List of publications and reserach products for the year 2026 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Journal Articles
A 20 MHz-BW 12.3-ENOB 3rd-Order Noise-Shaping SAR ADC with Multi-Input Architecture and PVT-Robust Ratio-Based FIA (Show >>)


List of publications and reserach products for the year 2025 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Recensioni su riviste
Editorial Special Section on High-Performance Frequency Synthesizers (Show >>)
Contributions on scientific books
Localized LO Phase Shifting for Phased Array Systems (Show >>)
Conference proceedings
34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning (Show >>)
A 10-GHz Localized-LO-Phase-Shifting Phased-Array Transmitter (Show >>)
A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3rd-order Multi-Input Filter and a PVT-Robust Ratio-Based FIA (Show >>)
A 28-38 GHz Digitally-Assisted Frequency Tripler with Background Calibration in 55nm SiGe BiCMOS (Show >>)
A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS (Show >>)
A 58.9fs-Jitter Fractional-N Digital PLL Using a Double-Edge Variable-Slope DTC (Show >>)
A Fractional-N Digital-PLL Based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under 3mVpp Supply Ripple (Show >>)
Journal Articles
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk (Show >>)
A 96.3% Efficient, 6mVpp Line Transient Response Time-Based Boost Converter With Feedback-PID for AMOLED Displays (Show >>)
A Low-Jitter Fractional-$N$ Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC (Show >>)
A Low-Jitter Fractional-N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology (Show >>)
A Low-Noise Digital PLL With an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators (Show >>)
A Low-Noise Fractional-$N$ Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC (Show >>)


List of publications and reserach products for the year 2024 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Patents
CONSTANT CHARGE CONTROL FOR DC-DC CONVERTERS in PFM (Show >>)
CONVERTITORE DI TENSIONE AVENTE PRESTAZIONI DI CONTROLLO MIGLIORATE (Show >>)
High Power Density and Efficiency Hybrid Interleaved DC-DC Converter with Continuous Conversion Ratio (Show >>)
Contributions on scientific books
D-band phased array antenna module for 5G backhaul (Show >>)
Digitally Intensive PLLs for mm-Wave FMCW Radars (Show >>)
Conference proceedings
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM (Show >>)
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion (Show >>)
A 260-A/48-V Bus Hybrid Resonant Converter with Large Conversion Ratio for Future Data Centers (Show >>)
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector (Show >>)
A 60 A Switched Tank Converter with Buck-Boost Sigma Regulation for 48 V Bus Down-Conversion (Show >>)
A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC (Show >>)
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique (Show >>)
A Wide Input Voltage Range Buck Converter with Constant-Charge PFM Control (Show >>)
Journal Articles
A 1-A 90% Peak Efficiency 5–36-V Input Voltage Time-Based Buck Converter with Adaptive Gain Compensation and Controlled-Skip Operation (Show >>)
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars (Show >>)
A High Power Density Quasi-Resonant Switched-Capacitor DC-DC Converter with Single Semi-Period Tank Current Modulation (Show >>)
A Wide-Input-Range Time-Based Buck Converter With Adaptive Gain and Continuous Phase Preset for Seamless PFM/PWM Transitions (Show >>)
Calibration Techniques in Phased-Locked Loops: Theoretical basis and practical applications (Show >>)
Hybrid Resonant Switched Tank Converters for High Step-Down Voltage Conversion (Show >>)
Insights on the Dynamic Performance of Nonminimum-Phase Boost Converters Exploiting Inductor-Current-Feedback RHPZ Mitigation (Show >>)


List of publications and reserach products for the year 2023 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Patents
METHOD FOR CONTROLLING A SINGLE INPUT DUAL OUTPUT DC-DC CONVERTER, CORRESPONDING CONVERTER AND COMPUTER PROGRAM PRODUCT (Show >>)
Conference proceedings
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering (Show >>)
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology (Show >>)
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS (Show >>)
A Compact Wide-Input-Range Time-Domain Buck Converter with Fast Transient Response for Industrial Applications (Show >>)
High Power Density 4:1 Resonant Switched-Capacitor DC-DC Converter for PoL Applications (Show >>)
Time-Based Buck Converter with Variable Frequency DCM and ON-Time Correction for Seamless Transitions (Show >>)
Journal Articles
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner (Show >>)
A Compact High-Efficiency Boost Converter With Time-Based Control, RHP Zero-Elimination, and Tracking Error Compensation (Show >>)
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering (Show >>)
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays (Show >>)
Integration of loop gain measurement circuit for stability evaluation in DC/DC converters with time-based control (Show >>)
Phase Noise Analysis of Periodically ON/OFF Switched Oscillators (Show >>)
Spread-Spectrum Frequency Modulation in a DC/DC Converter With Time-Based Control (Show >>)


List of publications and reserach products for the year 2022 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Recensioni su riviste
Special Section on the 47th IEEE European Solid-State Circuits Conference (ESSCIRC) (Show >>)
Patents
Circuito convertitore DC-DC e corrispondente procedimento di funzionamento (Show >>)
DC-DC CONVERTER APPARATUS WITH TIME-BASED CONTROL LOOP AND CORRESPONDING CONTROL METHOD, AND COMPUTER PROGRAM PRODUCT (Show >>)
RHPZ Mitigation Technique for DC-DC Non-minimum Phase Converter Operating in CCM (Show >>)
Conference proceedings
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters (Show >>)
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching (Show >>)
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler (Show >>)
A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation (Show >>)
A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters (Show >>)
Concurrent effect of redundancy and switching algorithms in SAR ADCs (Show >>)
Frequency Synthesizers for 5G Applications (Show >>)
Integrated Loop-Gain Measurement Circuit for DC/DC Boost Converters with Time-Based Control (Show >>)
Recent Advances in High-Performance Frequency Synthesizer Design (Show >>)
Journal Articles
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter (Show >>)
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping (Show >>)
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations (Show >>)
A Digital PLL with Multi-tap LMS-based Bandwidth Control (Show >>)
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time (Show >>)
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology (Show >>)
Hybrid Resonant Switched-Capacitor Converter for 48-3.4 V Direct Conversion (Show >>)
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise (Show >>)
manifesti v. 3.13.1 / 3.13.1
Area Servizi ICT
14/02/2026