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Information on didactic, research and institutional assignments on this page are certified by the University; more information, prepared by the lecturer, are available on the personal web page and in the curriculum vitae indicated on this webpage.
Information
LecturerZoni Davide
QualificationAssociate professor full time
Belonging DepartmentDipartimento di Elettronica, Informazione e Bioingegneria
Scientific-Disciplinary SectorIINF-05/A - Information Processing Systems
Curriculum VitaeDownload CV (520.06Kb - 20/12/2022)
OrcIDhttps://orcid.org/0000-0002-9951-062X

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DEIB - Edificio 201002---From :
To :
3496---Ricevimento studenti solo su appuntamento. inviare una email a davide.zoni [at] polimi.it
E-maildavide.zoni@polimi.it
Personal websitehttps://zoni.faculty.polimi.it/

Data source: RE.PUBLIC@POLIMI - Research Publications at Politecnico di Milano

List of publications and reserach products for the year 2025
No product yet registered in the year 2025


List of publications and reserach products for the year 2024 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
A Deep-Learning Technique to Locate Cryptographic Operations in Side-Channel Traces (Show >>)
A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS (Show >>)
Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms (Show >>)
Functional ISS-Driven Verification of Superscalar RISC-V Processors (Show >>)
Hound: Locating Cryptographic Primitives in Desynchronized Side-Channel Traces using Deep-Learning (Show >>)
ML-Assisted Attack Detection on NoC-Based Many-Cores Through On-Chip Traffic Monitoring (Show >>)
Rethinking the Switch Architecture for Stateful In-network Computing (Show >>)
The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs (Show >>)
The TEXTAROSSA Project: Cool all the Way Down to the Hardware (Show >>)
Journal Articles
A Deep Learning-assisted Template Attack Against Dynamic Frequency Scaling Countermeasures (Show >>)
Design-time methodology for optimizing mixed-precision CPU architectures on FPGA (Show >>)


List of publications and reserach products for the year 2023 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE (Show >>)
Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments (Show >>)
HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs (Show >>)
Hardware and Software Support for Mixed Precision Computing: A Roadmap for Embedded and HPC Systems (Show >>)
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project (Show >>)
Journal Articles
A survey on run-time power monitors at the edge (Show >>)


List of publications and reserach products for the year 2022 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
FPGA implementation of BIKE for quantum-resistant TLS (Show >>)
Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators (Show >>)
On the Effectiveness of True Random Number Generators Implemented on FPGAs (Show >>)
On the use of hardware accelerators in QC-MDPC code-based cryptography (Show >>)
Journal Articles
Cost-effective fixed-point hardware support for RISC-V embedded systems (Show >>)
Design of side-channel resistant power monitors (Show >>)
Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems (Show >>)
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators (Show >>)
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach (Show >>)


List of publications and reserach products for the year 2021 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Patents
A COMPUTING PLATFORM AND METHOD FOR SYNCHRONIZE THE PROTOTYPE EXECUTION AND SIMULATION OF HARDWARE DEVICE (Show >>)
A COMPUTING PLATFORM FOR PREVENTING SIDE CHANNEL ATTACKS (Show >>)
Conference proceedings
Integrating Side Channel Security in the FPGA Hardware Design Flow (Show >>)
TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale (Show >>)
Journal Articles
An FPU design template to optimize the accuracy-efficiency-area trade-off (Show >>)
Automatic identification and hardware implementation of a resource-constrained power model for embedded systems (Show >>)
manifesti v. 3.9.3 / 3.9.3
Area Servizi ICT
30/04/2025