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Information on didactic, research and institutional assignments on this page are certified by the University; more information, prepared by the lecturer, are available on the personal web page and in the curriculum vitae indicated on this webpage.
Information
LecturerSamori Carlo
QualificationFull professor full time
Belonging DepartmentDipartimento di Elettronica, Informazione e Bioingegneria
Scientific-Disciplinary SectorIINF-01/A - Electronics
Curriculum VitaeDownload CV (70.29Kb - 17/05/2019)
OrcIDhttps://orcid.org/0000-0002-7084-0721

Contacts
Office hours
DepartmentFloorOfficeDayTimetableTelephoneFaxNotes
Dei - Sede di Via Golgi 40secondo2.16MondayFrom 14:30
To 16:30
0223993732------
E-mailcarlo.samori@polimi.it
Personal website---

Data source: RE.PUBLIC@POLIMI - Research Publications at Politecnico di Milano

List of publications and reserach products for the year 2025 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
A Complementary Bootstrapped Sampler for High-Frequency High-Resolution ADCs (Show >>)
Power-Reduction Technique for Time-to-Digital Converters in 28-nm CMOS process (Show >>)
Journal Articles
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk (Show >>)


List of publications and reserach products for the year 2024 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM (Show >>)
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion (Show >>)
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector (Show >>)
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique (Show >>)
A Highly Energy-Efficient FIA-based AZ-free Ring Amplifier for Pipeline-SAR ADCs (Show >>)
Journal Articles
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars (Show >>)
A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC with Charge Linearization (Show >>)


List of publications and reserach products for the year 2023 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering (Show >>)
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology (Show >>)
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS (Show >>)
Journal Articles
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner (Show >>)
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering (Show >>)
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays (Show >>)


List of publications and reserach products for the year 2022 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters (Show >>)
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching (Show >>)
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler (Show >>)
Concurrent effect of redundancy and switching algorithms in SAR ADCs (Show >>)
Journal Articles
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter (Show >>)
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping (Show >>)
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations (Show >>)
A Digital PLL with Multi-tap LMS-based Bandwidth Control (Show >>)
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time (Show >>)
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise (Show >>)


List of publications and reserach products for the year 2021 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays (Show >>)
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter (Show >>)
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability (Show >>)
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter (Show >>)
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity (Show >>)
Digital PLLs: The modern timing reference for radar and communication systems (Show >>)
SiGe BiCMOS Building Blocks for E- and D-Band Backhauling Front-Ends (Show >>)
Journal Articles
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs (Show >>)
A Novel Topology of Coupled Phase-Locked Loops (Show >>)
manifesti v. 3.9.3 / 3.9.3
Area Servizi ICT
24/04/2025