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Information on didactic, research and institutional assignments on this page are certified by the University; more information, prepared by the lecturer, are available on the personal web page and in the curriculum vitae indicated on this webpage.
Information
LecturerPilato Christian
QualificationAssociate professor full time
Belonging DepartmentDipartimento di Elettronica, Informazione e Bioingegneria
Scientific-Disciplinary SectorIINF-05/A - Information Processing Systems
Curriculum VitaeDownload CV (189.33Kb - 02/03/2023)
OrcIDhttps://orcid.org/0000-0001-9315-1788

Contacts
Office hoursOffice hours is not available yet
E-mailchristian.pilato@polimi.it
Personal websitehttp://pilato.faculty.polimi.it

Data source: RE.PUBLIC@POLIMI - Research Publications at Politecnico di Milano

List of publications and reserach products for the year 2025
No product yet registered in the year 2025


List of publications and reserach products for the year 2024 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach (Show >>)
Journal Articles
QHLS: An HLS Framework to Convert High-Level Descriptions to Quantum Circuits (Show >>)
Using Static Analysis for Enhancing HLS Security (Show >>)


List of publications and reserach products for the year 2023 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization (Show >>)
Message from the Program Chairs: ICCD 2023 (Show >>)
Towards High-Level Synthesis of Quantum Circuits (Show >>)
Editorship of scientific books
Embedded Computer Systems: Architectures, Modeling, and Simulation (Show >>)
Journal Articles
A Survey of FPGA Optimization Methods for Data Center Energy Efficiency (Show >>)
Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics (Show >>)
Generating Posit-Based Accelerators With High-Level Synthesis (Show >>)
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction (Show >>)
Optimizing the Use of Behavioral Locking for High-Level Synthesis (Show >>)


List of publications and reserach products for the year 2022 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Contributions on scientific books
Protecting Hardware IP Cores During High-Level Synthesis (Show >>)
Conference proceedings
A Composable Design Space Exploration Framework to Optimize Behavioral Locking (Show >>)
ALICE: An Automatic Design Flow for eFPGA Redaction (Show >>)
Designing ML-resilient locking at register-transfer level (Show >>)
HOLL: Program Synthesis for Higher Order Logic Locking (Show >>)
High-Level Methods for Hardware IP Protections: Solutions, Trends, and Challenges (Show >>)
Invited: High-level design methods for hardware security: Is it the right choice? (Show >>)
Message from the Program Chairs: ICCD 2022 (Show >>)
Reconfigurable logic for hardware IP protection: Opportunities and challenges (Show >>)
Journal Articles
Dynamically-Tunable Dataflow Architectures Based on Markov Queuing Models (Show >>)
Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications (Show >>)


List of publications and reserach products for the year 2021 (Show all details | Hide all details)
Type Title of the Publicaiton/Product
Conference proceedings
Compiler Infrastructure for Specializing Domain-Specific Memory Templates (Show >>)
EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms (Show >>)
Exploring eFPGA-based Redaction for IP Protection (Show >>)
Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks (Show >>)
From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics (Show >>)
High-Level Synthesis of Security Properties via Software-Level Abstractions (Show >>)
Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications (Show >>)
Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis (Show >>)
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? (Show >>)
Journal Articles
A Survey on Domain-Specific Memory Architectures (Show >>)
ASSURE: RTL Locking Against an Untrusted Foundry (Show >>)
Automatic Generation of Heterogeneous SoC Architectures with Secure Communications (Show >>)
CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching (Show >>)
manifesti v. 3.9.3 / 3.9.3
Area Servizi ICT
24/04/2025